Expedite Technology Solutions LLC

US_West | Electrical/Electronics & Semiconductors Engineer_L2

SANTA CLARA, CAPosted a month ago

Job summary

  • Job post source

    This job is from a recruiting firm hiring for a separate company based on the language about candidate submission, interview process, and travel reimbursement policies.

  • Job overview

    The role is for an Analog Layout Engineer with 7+ years of experience in analog and RF layout, focusing on advanced CMOS FinFET technologies for high-speed and ultra-low power applications.

  • Responsibilities and impact

    The engineer will develop and lead complex IC layout designs at block and chip levels, work with high-performance analog mixed-signal blocks, perform floor planning, block-level routing, and top-level chip assembly, and apply layout techniques considering thermal and electro-migration effects.

  • Experience and skills

    Requires minimum 7+ years in analog and RF layout, experience with advanced CMOS FinFET technologies (7nm, 5nm, 3nm), proficiency with Cadence, Mentor, and Synopsys EDA tools, and knowledge of Python is preferred.

  • Job location and travel

    The position is located in Santa Clara, CA, with possible travel to client or offsite locations for onboarding and meet and greet sessions.

  • Application process

    Candidates must submit legal name, photo ID, Skype ID for a mandatory video interview, and other personal details; a meet and greet is required before starting the assignment.

  • Unique job features

    The job involves working with cutting-edge IC layout technologies in advanced CMOS FinFET nodes (7nm, 5nm, 3nm) and complex analog mixed-signal blocks, with travel and onboarding protocols unique to this role.

Company overview

Expedite Technology Solutions specializes in providing comprehensive IT services, including cloud computing, cybersecurity, and data analytics, to businesses across various industries. They generate revenue through consulting, managed services, and software solutions tailored to client needs. Founded in 2005, the company has grown rapidly, establishing a reputation for innovative technology solutions and exceptional customer service. Key milestones include strategic partnerships with major tech firms and consistent recognition in industry awards for their cutting-edge solutions.

How to land this job

  • Tailor your resume to emphasize your 7+ years of experience in analog and RF layout design, specifically highlighting your work with advanced CMOS FinFET technologies such as 7nm and 3nm.

  • Highlight your expertise with industry-standard EDA tools like Cadence, Mentor, and Synopsys, and your experience in high-speed analog mixed-signal block layouts including TIAs, CMOS drivers, data converters, and PLLs.

  • Apply through multiple platforms including Expedite Technology Solutions LLC's corporate website and LinkedIn to increase your chances of being noticed for this role.

  • Connect with engineers and recruiters in the analog layout or semiconductor divisions at Expedite Technology Solutions LLC on LinkedIn, using ice breakers like commenting on recent technology advancements in FinFET processes or asking about their experience with 3nm chip design.

  • Optimize your resume for ATS by including keywords such as 'Analog Layout Design,' 'CMOS FinFET,' 'EDA tools,' 'TSMC 7nm/5nm/3nm,' and 'high-speed mixed-signal IC' to ensure your application passes initial screenings.

  • Use Jennie Johnson's Power Apply feature to automate applying across multiple platforms, tailor your resume with relevant keywords, and identify LinkedIn contacts to connect with, allowing you to focus more on preparing for interviews and networking.

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