Job summary
Job overview
The Principal Mixed Signal Design Verification Engineer at Astera Labs leads verification of complex high-speed SerDes silicon products, ensuring their functionality and performance in AI and cloud infrastructure applications.
Responsibilities and impact
The role involves developing and executing verification test plans using UVM and C/C++, integrating high-level programming with System Verilog environments, automating verification infrastructure with scripting, debugging RTL designs, and collaborating with firmware teams for end-to-end mixed signal verification.
Experience and skills
Candidates must have a strong electrical engineering background with at least 8 years in high-speed SerDes product verification, proficiency in UVM, System Verilog, C/C++, scripting languages, and experience with Matlab/Simulink integration, channel modeling, and firmware verification; a Bachelor's degree is required, Master's preferred.
Work environment and culture
Astera Labs values innovation, diversity, and an entrepreneurial mindset, encouraging creativity and inclusion of diverse backgrounds in a dynamic, customer-focused environment.
Company information
Astera Labs is a global leader in connectivity solutions for AI and cloud infrastructure, offering semiconductor products and software tools that enable scalable, customizable architectures for data centers and hyperscalers.
Job location and travel
The position requires authorization to work in the US and immediate availability, implying a US-based role; remote work or office specifics are not detailed.
Unique job features
The job features advanced mixed signal verification with hybrid directed and constrained random environments, integration of software and firmware verification, and opportunities to work on cutting-edge PCIe, Ethernet, and SerDes technologies.
Company overview
Astera Labs specializes in designing purpose-built connectivity solutions for data-centric systems, focusing on overcoming performance bottlenecks in data centers. They generate revenue through the sale of advanced semiconductor products that enhance data flow efficiency and reliability. Founded in 2017, the company has quickly gained traction with its innovative approach to solving complex data challenges, securing significant funding and partnerships with leading technology firms.
How to land this job
Position your resume to highlight your expertise in UVM and C/C++ verification methodologies, emphasizing your experience integrating high-level programming with SystemVerilog environments, as this is central to the role at Astera Labs.
Focus on showcasing your background with high-speed SerDes and silicon product verification for server, storage, or networking applications, along with your ability to develop test plans and use scripting tools like Perl and Python to automate verification tasks.
Apply through multiple channels including Astera Labs’ official corporate careers page and LinkedIn to maximize your visibility and chances of getting noticed by their recruiting team.
Connect on LinkedIn with engineers and hiring managers in Astera Labs’ design verification or mixed-signal teams; start conversations by referencing recent Astera Labs product launches or asking about their approach to integrating PCIe and Ethernet verification.
Optimize your resume for ATS by incorporating key terms such as 'UVM,' 'SystemVerilog,' 'SerDes verification,' 'Matlab/Simulink integration,' 'PCIe,' and 'emulation' to ensure your resume passes automated filters effectively.
Leverage Jennie Johnson’s Power Apply feature to automate tailored applications, identify multiple application sources, and find relevant Astera Labs contacts on LinkedIn, allowing you to focus your energy on preparing for interviews and networking.
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