Silicon DV Engineer III

BURLINGAME, CAPosted 24 days ago

Job summary

• Job post source

  This job is directly from Iron Systems, Inc

• Job overview

  The Silicon DV Engineer III at Iron Systems, Inc is responsible for low power verification and ensuring functional, code, and power coverage in silicon design verification, impacting product quality and performance.

• Responsibilities and impact

  The role involves low power verification, writing and augmenting test plans, implementing testbenches and checkers, debugging test failures, and collaborating with designers and architects to resolve issues.

• Experience and skills

  Requires 7+ years of DV engineering experience, strong skills in SystemVerilog, UVM, Synopsys VCS/Verdi or Cadence Incisive tools, UPF simulation flow, and C/C++. Preferred skills include FPGA validation, ASIC design, scripting in Tcl/Python, and advanced verification techniques.

• Work environment and culture

  Iron Systems values innovation and customer focus, providing a collaborative environment for engineering and problem solving.

• Company information

  Iron Systems, Inc is a provider of custom-built computing infrastructure platforms with over 15 years of experience in design, engineering, manufacturing, and global support services.

• Job location and travel

  The position is located in Burlingame, California, USA.

• Unique job features

  The job features specialized work in low power verification using advanced methodologies like UPF, UVM, and power-aware verification flows.

Company overview

Iron Systems is a global provider of integrated systems, data center infrastructure, and support services. They specialize in designing, manufacturing, and deploying customized hardware solutions for cloud computing, data centers, and enterprise IT environments. The company generates revenue through the sale of its hardware products, professional services, and managed support services. Founded in 2002, Iron Systems has built a reputation for delivering high-quality, scalable solutions tailored to meet the specific needs of their clients, including some of the world's leading technology companies.

How to land this job

• Tailor your resume to emphasize your 7+ years of experience in design verification with strong expertise in SystemVerilog, UVM, and low power verification methodologies such as UPF and power-aware simulation flows like VC LP and VCS NLP.

• Highlight your hands-on skills in developing executable test plans, coverage-driven verification, and familiarity with Synopsys VCS, Verdi, or Cadence Incisive tools, as these are critical for the Silicon DV Engineer III role at Iron Systems, Inc.

• Apply through multiple channels including Iron Systems' official corporate career page and LinkedIn postings to maximize your visibility and chances of consideration for the position.

• Connect on LinkedIn with engineers and hiring managers in Iron Systems' verification or silicon engineering divisions; initiate conversations by referencing recent Iron Systems projects, asking about their approach to low power verification challenges, or expressing enthusiasm for their innovative computing infrastructure solutions.

• Optimize your resume for ATS by incorporating keywords from the job description such as 'SystemVerilog', 'UVM', 'low power verification', 'UPF', 'coverage-driven verification', and 'Synopsys VCS' to ensure it passes automated screening and reaches recruiters.

• Utilize Jennie Johnson's Power Apply feature to automate tailoring your resume, identify multiple application portals, and find relevant Iron Systems contacts on LinkedIn, freeing you to focus on preparing for interviews and networking effectively.