Job summary
Job post source
This job is from a recruiting firm hiring for a separate company as indicated by the contract nature and detailed technical requirements.
Job overview
The Senior Design Engineer role focuses on fullchip and block-level SDC development and static timing analysis to ensure timing closure in ASIC designs.
Responsibilities and impact
The engineer will manage fullchip SDCs, collaborate with physical design and DFT teams, develop methodologies for SDC promotion and correctness, review block-level SDCs, and create clocking diagrams and documentation.
Experience and skills
Candidates need a Bachelor's or Master's in Electrical or Computer Engineering with 5-7+ years in ASIC design, strong experience in SDC development, static timing analysis with PrimeTime/Tempus, synthesis tools, constraint analyzers, formal verification, and scripting languages like Python or TCL.
Job location and travel
The position is located onsite in San Jose, CA, requiring day-one presence.
Unique job features
The role uniquely bridges design and physical design teams, requiring strong digital design fundamentals and hands-on timing constraint expertise.
Company overview
Prismagic Solutions Inc. is a company based in San Jose, California, that operates in the technology sector, specifically focusing on ASIC (Application-Specific Integrated Circuit) and FPGA (Field-Programmable Gate Array) design engineering. The company appears to provide specialized engineering services, likely catering to clients in industries such as semiconductors and electronics. Its business model revolves around offering expert design and development solutions for custom hardware, enabling clients to accelerate product innovation and meet specific technical requirements. While detailed company history is not available, Prismagic Solutions Inc. is positioned within the competitive Silicon Valley market, emphasizing advanced engineering talent and technical expertise.
How to land this job
Position your resume to highlight your expertise in fullchip and block-level SDC development, emphasizing your hands-on experience with Static Timing Analysis using PrimeTime and Tempus tools.
Focus on showcasing your ability to collaborate across design, physical design, and DFT teams to close fullchip timing in multiple modes, as well as your skills in creating and reviewing clocking diagrams and SDC documentation.
Apply through multiple channels including Prismagic Solutions Inc.'s corporate career page, LinkedIn job postings, and specialized contract engineering job boards to maximize your application visibility.
Connect with engineers and managers in the ASIC design and physical design divisions at Prismagic Solutions Inc. on LinkedIn; use ice breakers like commenting on recent company projects, asking about challenges in fullchip timing closure, or inquiring about their experience with STA tools.
Optimize your resume for ATS by incorporating keywords such as 'Static Timing Analysis,' 'PrimeTime,' 'Tempus,' 'SDC development,' 'clocking diagrams,' 'Synopsys DC,' and 'Python scripting' to ensure it passes automated screenings.
Utilize Jennie Johnson's Power Apply feature to automate tailoring your resume, applying through the best channels, and identifying relevant LinkedIn contacts, allowing you to focus your time on preparing for interviews and networking effectively.
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