Job summary
Job post source
This job is directly from Ouster
Job overview
The Lead FPGA Engineer at Ouster will lead FPGA/ASIC design and verification efforts, focusing on achieving functional safety certification in compliance with ISO26262 / ASIL-B specifications.
Responsibilities and impact
Responsibilities include leading safety analysis of FPGA subsystems, creating functional safety documentation, developing and integrating features across the FPGA stack, enforcing FPGA development processes, and performing hands-on laboratory work for troubleshooting.
Experience and skills
Candidates should have a Bachelor's in Computer Engineering or Electrical Engineering, with at least 5 years of FPGA development experience and proficiency in RTL development using Verilog and SystemVerilog.
Company information
Ouster Inc. specializes in digital hardware design, focusing on FPGA/ASIC development and functional safety certification.
Company overview
Ouster is a leading provider of high-resolution digital lidar sensors used in various industries, including automotive, industrial automation, smart infrastructure, and robotics. They generate revenue by selling their advanced lidar technology, which enhances the capabilities of autonomous vehicles, industrial machinery, and smart city applications. Founded in 2015, Ouster has rapidly grown due to its innovative approach to lidar technology, leveraging digital architecture to deliver superior performance and reliability. Key milestones include their public listing via a SPAC merger in 2021, which has bolstered their financial position and market presence.
How to land this job
Tailor your resume to showcase your extensive experience in FPGA/ASIC design, emphasizing your hands-on skills in RTL design, verification, and hardware bring-up, which are critical for the Lead FPGA Engineer role at Ouster.
Highlight your knowledge and experience with functional safety standards, particularly ISO 26262 and ASIL-B, as well as your ability to create functional safety documentation and perform safety analysis of FPGA subsystems.
Apply through multiple platforms, including Ouster's corporate website and LinkedIn, to maximize your visibility and chances of landing an interview for this position.
Connect with professionals in the firmware division at Ouster on LinkedIn to learn more about the role and the team; potential ice breakers could include discussing a recent project they worked on or asking for their insights on the company's approach to FPGA safety certification.
Optimize your resume for ATS by including relevant keywords such as 'FPGA development', 'RTL design', 'ISO 26262', and 'safety analysis', ensuring it aligns with the job description to pass initial screenings.
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