Job summary
Job post source
This job is from a recruiting firm hiring for a separate company based on the contract nature and the company name Creospan Inc., which is known as a staffing and recruiting firm.
Job overview
The Design Verification Engineer role involves leading low power verification efforts to ensure functional, code, and power coverage in silicon design projects, impacting product quality and reliability.
Responsibilities and impact
The engineer will write and update test plans, implement testbenches and checkers, execute test sequences, debug failures, and collaborate with designers and architects to resolve issues, ensuring thorough verification coverage.
Experience and skills
Candidates must have 7+ years of DV engineering experience, proficiency in SystemVerilog, UVM, Synopsys VCS/Verdi or Cadence tools, UPF simulation flow, and 2+ years in C/C++. Preferred skills include FPGA validation, scripting languages, ASIC design, formal verification, and a relevant master's degree.
Company information
Creospan Inc. is a staffing and recruiting company specializing in technology roles, facilitating contract placements for other companies.
Job location and travel
The position is remote with a 12-month contract duration.
Unique job features
The role focuses on low power verification with advanced methodologies like coverage driven verification and power aware GLS flow, requiring collaboration across multiple technical teams.
Company overview
Creospan Inc. is a technology consulting and solutions company specializing in IT services, software development, and business process outsourcing. They generate revenue by providing customized technology solutions to clients across various industries, including telecommunications, healthcare, and finance. Founded in 1999, Creospan has grown by focusing on innovation and client-centric approaches, establishing a reputation for delivering high-quality, scalable solutions. Their expertise in emerging technologies and commitment to excellence make them a significant player in the tech consulting space.
How to land this job
Position your resume to highlight over 7 years of hands-on experience in design verification engineering, emphasizing your expertise with SystemVerilog (SV) and Universal Verification Methodology (UVM).
Focus on showcasing your proficiency in low power verification, executable test plans, coverage-driven verification, and experience with Synopsys VCS, Verdi, or Cadence Incisive tools, as these are critical for this role at Creospan Inc.
Apply through multiple channels including Creospan Inc.'s corporate careers page, LinkedIn job postings, and other reputable job boards to maximize your application visibility.
Connect with current Design Verification Engineers or hiring managers at Creospan Inc. on LinkedIn; open conversations by referencing recent projects in low power verification or asking about their experience with UPF simulation flows to break the ice.
Optimize your resume for ATS by incorporating keywords from the job description such as 'low power verification,' 'SystemVerilog,' 'UVM,' 'coverage-driven verification,' 'Synopsys VCS,' and 'UPF simulation,' ensuring your resume passes automated screenings effectively.
Utilize Jennie Johnson's Power Apply feature to automate tailored applications, identify multiple application portals, and find relevant LinkedIn contacts, allowing you to focus your energy on interview preparation and networking.
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