Job summary
Job post source
This job is directly from Astera Labs
Job overview
The Principal Digital Design Engineer at Astera Labs leads the development of advanced high-speed SerDes wireline and optical transceivers for AI systems, impacting the company's connectivity solutions for AI and cloud infrastructure.
Responsibilities and impact
The role involves designing critical digital blocks from architecture to RTL delivery, collaborating with DSP Architecture, PD, and DV teams to optimize power, latency, and performance, and resolving design issues through the full design cycle.
Experience and skills
Requires a Bachelor's or Master's in Electrical/Computer Engineering or related field, 5-10 years in high-speed DSP digital design, proficiency in System Verilog, experience with EDA tools, and full design cycle expertise; preferred experience includes 100G+ PAM4 DSP SerDes and PAM4 DSP block design.
Work environment and culture
Astera Labs values diversity and inclusion, encouraging applicants from varied backgrounds including underrepresented groups, fostering creativity and innovation.
Company information
Astera Labs is a global leader in connectivity solutions integrating PCIe, CXL, Ethernet, and software tools to enable scalable, customizable AI and cloud infrastructure architectures.
Team overview
The candidate will join the DSP SerDes team working on pivotal projects for high-speed transceiver development.
Unique job features
The job offers the opportunity to work on cutting-edge high-speed DSP SerDes technology for AI systems, involving complex design challenges and collaboration across architecture, physical design, and verification teams.
Company overview
Astera Labs specializes in designing purpose-built connectivity solutions for data-centric systems, focusing on overcoming performance bottlenecks in data centers. They generate revenue through the sale of advanced semiconductor products that enhance data flow efficiency and reliability. Founded in 2017, the company has quickly gained traction with its innovative approach to solving complex data challenges, securing significant funding and partnerships with leading technology firms.
How to land this job
Position your resume to emphasize your expertise in high-speed digital design, particularly in DSP data paths and System Verilog coding, aligning with Astera Labs' focus on advanced SerDes wireline and optical transceivers.
Highlight your experience managing critical design blocks from architecture through tapeout, showcasing your skills in timing fixes, power and area optimization, and silicon issue resolution as detailed in the job description.
Apply through multiple channels such as the Astera Labs corporate career page and LinkedIn to maximize your application visibility and ensure you reach the right hiring teams.
Connect with engineers and managers in the DSP SerDes or digital design teams at Astera Labs on LinkedIn; use ice breakers like commenting on recent Astera Labs innovations in AI connectivity or asking about the challenges in developing 100G+ PAM4 DSP SerDes.
Optimize your resume for ATS by including keywords like 'System Verilog,' 'DSP data path,' 'SerDes,' 'timing fixes,' 'power optimization,' and 'RTL delivery' to pass automated screening effectively.
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