BURLINGTON, VTPosted 30+ days ago

Job summary

• Job post source

  This job is directly from Technical-Link N. America

• Job overview

  The Physical Design Engineer role involves performing synthesis, place and route, clock tree synthesis, routing, power-signal integrity, and physical verification to ensure timing closure on complex logic blocks, contributing to the company's chip design and optimization efforts.

• Responsibilities and impact

  The engineer will handle timing and logic ECOs, collaborate with RTL design teams to resolve congestion and timing issues, and address partition and chip-level challenges in a collaborative environment.

• Experience and skills

  Candidates should have a Bachelor’s degree in Computer Science or Electrical Engineering with 5-10 years of experience or a Master’s/PhD with 3-5 years, strong knowledge of RTL to GDS flows, PD optimization, complex IP placement, EDA tools like Cadence Innovus and Synopsys Fusion Compiler, scripting skills in Perl, Tcl, Python, and understanding of digital logic and Verilog/VHDL.

• Work environment and culture

  The role is set in a collaborative and innovative environment encouraging teamwork and self-discipline.

Company overview

Technical-Link N. America is a specialized staffing and recruitment firm that focuses on connecting skilled professionals with opportunities in the engineering and technology sectors. They generate revenue by providing recruitment services to companies in need of technical talent, earning fees for successful placements. The company has established a strong reputation for its expertise in matching candidates with roles that align with their skills and career goals. Candidates should be aware that Technical-Link N. America emphasizes building long-term relationships with both clients and candidates, ensuring a personalized and effective recruitment process.

How to land this job

• Tailor your resume to highlight your expertise in physical design engineering, specifically emphasizing your experience with synthesis, place and route, clock tree synthesis, timing analysis, and closure on complex logic blocks.

• Focus on showcasing your proficiency with EDA tools like Cadence Innovus and Synopsys Fusion Compiler, as well as your scripting skills in Perl, Tcl, and Python, to align with the job’s technical requirements.

• Apply through multiple platforms including Technical-Link N. America’s corporate career site and LinkedIn to maximize your application’s exposure and increase your chances of being noticed.

• Connect with current employees in the physical design or engineering division at Technical-Link N. America on LinkedIn; start conversations by complimenting recent projects or asking about challenges in timing closure and congestion management.

• Optimize your resume for ATS by incorporating keywords such as 'physical design,' 'synthesis,' 'clock tree synthesis,' 'EDA tools,' 'timing analysis,' and 'routing' to ensure it passes automated screenings effectively.

• Utilize Jennie Johnson’s Power Apply feature to automate tailored applications, find multiple job posting sites, and identify LinkedIn contacts, freeing you to focus on interview preparation and networking.